1. Field of the Invention
The present invention relates generally to methods for fabricating dielectric layers employed within microelectronics fabrications. More particularly, the present invention relates to methods for fabricating comparatively low dielectric constant dielectric layers employed within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics integration levels have increased and patterned microelectronics conductor layer linewidth dimensions have decreased, it has become more common within the art of microelectronics fabrication to employ low dielectric constant dielectric layers formed interposed between the patterns of patterned microelectronics conductor layers within microelectronics fabrications. Low dielectric constant dielectric layers are desirable interposed between the patterns of patterned microelectronics conductor layers within microelectronics fabrications since such low dielectric constant dielectric layers typically provide microelectronics fabrications with enhanced microelectronics fabrication speed, reduced microelectronics fabrication parasitic capacitance and attenuated patterned microelectronics conductor layer cross-talk.
Of the methods and materials which may be employed for forming low dielectric constant dielectric layers interposed between the patterns of patterned microelectronics conductor layers within microelectronics fabrications, methods which provide dielectric layers which in turn define vacuum evacuated or gas filled (such as but not limited to air filled) voids interposed between the patterns of patterned microelectronics conductor layers are particularly desirable within the art of microelectronics fabrication. Such methods are desirable since vacuum evacuated or gas filled voids typically yield within a microelectronics fabrication a dielectric layer possessing in the pertinent locations interposed between a series of patterns which comprises a patterned microelectronics conductor layer a dielectric constant approaching a theoretical lower limit of 1.0. For comparison purposes, conventional silicon containing dielectric layers formed of silicon containing dielectric materials such as but not limited to silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials typically exhibit homogeneous dielectric constants within a range of from about 4.0 to about 4.4. Similarly, alternative low dielectric constant dielectric layers formed from low dielectric constant dielectric materials such as but not limited to organic polymer spin-on-polymer dielectric materials (such as but not limited to polyimide organic polymer spin-on-polymer dielectric materials, poly (arylene ether) organic polymer spin-on-polymer dielectric materials and fluorinated poly (arylene ether) organic polymer spin-on-polymer dielectric materials), amorphous carbon dielectric materials and silsesquioxane spin-on-glass (SOG) dielectric materials (such as but not limited to hydrogen silsesquioxane spin-on-glass (SOG) dielectric materials, carbon bonded hydrocarbon silsesquioxane spin-on-glass (SOG) dielectric materials and carbon bonded fluorocarbon silsesquioxane spin-on-glass (SOG) dielectric materials) typically exhibit somewhat lower homogeneous dielectric constants in a range of from about 2.5 to about 3.3.
It is therefore towards the goal of forming within microelectronics fabrications low dielectric constant dielectric layers which define, at least in part, vacuum evacuated or gas filled voids interposed between the patterns of patterned conductor layers upon which are formed those low dielectric constant dielectric layers, that the present invention is more generally directed.
Various methods and associated microelectronics structures have been disclosed within the art of microelectronics fabrication for forming upon patterned microelectronics conductor layers within microelectronics fabrications microelectronics dielectric layers which at least in part define vacuum evacuated or gas filled voids interposed between the patterns which comprise patterned conductor layers within microelectronics fabrications.
For example, Machida, in Japan Patent No. 63-98134(A), discloses an integrated circuit microelectronics fabrication having formed therein upon a patterned conductor layer a low dielectric constant dielectric layer in turn having formed therein a series of voids interposed between the patterns which comprise the patterned conductor layer. Within the integrated circuit microelectronics fabrication so formed, a capacitance of the patterns which comprise the patterned conductor layer is reduced even under circumstances where a thickness of a second dielectric layer upon which is formed the patterned conductor layer is equal to a separation distance of the patterns which comprise the patterned conductor layer.
In addition, and analogously with Machida, Koyama, in Japan Patent No. 2-151032(A), discloses an integrated circuit microelectronics fabrication also having formed therein upon a patterned conductor layer a low dielectric constant dielectric layer which defines a series of voids interposed between a series of patterns which comprises the patterned conductor layer. The voids are sealed within the low dielectric constant dielectric layer in a fashion such that an encapsulating resin subsequently formed upon the low dielectric constant dielectric layer is substantially precluded from permeating into the voids.
Further, Lien et al., in U.S. Pat. No. 5,310,700, discloses another analogous method for forming within an integrated circuit microelectronics fabrication a low dielectric constant dielectric layer over a patterned conductor layer, where the low dielectric constant dielectric layer defines a series of voids formed interposed between a series of patterns which comprises the patterned conductor layer. The method may employ a patterned hard mask layer formed upon, and wider than, the patterned conductor layer, in order to more readily form the series of voids when forming the low dielectric constant dielectric layer.
Still further, Stoltz et al., in U.S. Pat. No. 5,407,860, discloses a method for defining a series of voids interposed between a series of patterns which comprises a patterned conductor layer within an integrated circuit microelectronics fabrication when forming upon the patterned conductor layer within the integrated circuit microelectronics fabrication a dielectric layer. The method employs a non-wetting material formed upon at least the sidewalls of the series of patterns which comprises the patterned conductor layer but not completely occupying the spaces between the series of patterns which comprises the patterned conductor layer nor upon the top surfaces of the series of patterns which comprises the patterned conductor layer. Thus, when a dielectric layer is subsequently formed upon the patterned conductor layer having the non-wetting material selectively formed upon portions of its patterns there is formed a series of voids beneath the dielectric layer, where the series of voids is formed interposed between the series of patterns which comprises the patterned conductor layer.
Still yet further, Fitch et al., in U.S. Pat. No. 5,510,645, discloses several additional methods, and structures formed therefrom, for defining a series of voids interposed between a series of patterns which comprises a patterned conductor layer within an integrated circuit microelectronics fabrication when forming upon the patterned conductor layer within the integrated circuit microelectronics fabrication a dielectric layer. The methods employ selective etching to remove sacrificial layers formed interposed between the series of patterns which comprises the patterned conductor layer, thus forming voids in locations previously occupied by the sacrificial layers.
Finally, although related more specifically to attenuating void formation within dielectric layers formed interposed between the patterns which comprise patterned conductor layers within integrated circuit microelectronics fabrications rather than promoting void formation within dielectric layers formed interposed between the patterns which comprise patterned conductor layers within integrated circuit microelectronics fabrications, Jang et al., in U.S. Pat. No. 5,536,681, also discloses a method pertinent to the present invention. The method employs a selective nitrogen plasma treatment of upper lying portions of a conformal silicon oxide liner layer formed upon a patterned conductor layer within an integrated circuit microelectronics fabrication, such that there is attenuated formation of voids interposed between the patterns which comprise the patterned conductor layer when there is subsequently formed upon the selectively nitrogen plasma treated conformal silicon oxide liner layer a gap filling dielectric layer formed employing an ozone assisted thermal chemical vapor deposition (CVD) method employing tetraethylorthosilicate (TEOS) as a silicon source material.
Desirable in the art of microelectronics fabrication are additional methods and materials which may be employed for forming a dielectric layer over a patterned microelectronics layer within a microelectronics fabrications, such that a series of vacuum evacuated or gas filled voids is defined interposed between a series of patterns which comprises the patterned microelectronics layer when forming the dielectric layer over the patterned microelectronics layer. More particularly desirable in the art of integrated circuit microelectronics fabrication are additional methods and materials which may be employed for forming a dielectric layer over a patterned conductor layer within an integrated circuit microelectronics fabrication, such that a series of vacuum evacuated or gas filled voids is formed interposed between a series of patterns which comprises the patterned conductor layer when forming the dielectric layer over the patterned conductor layer.
It is towards the foregoing goals that the present invention is both generally and more specifically directed.